|Title:||Lecturer - Computer Science|
TIMOTHY DARYL STANLEY, PhD EE
Home (801-607-1929) Work (801-863-5088)
1868 South 45 West, Orem, Utah 84058
Professional Objective - Share my breath of experience from industry and academia with university students to help them be successful in their careers and lives, and develop publishable research projects with students.
PhD Electrical Engineering University of New Mexico Jul 1985
Dissertation: "The Effect of Operating Frequency in the Radiation Induced Build-Up of Trapped Holes and Interface States in MOS Devices”
MS Nuclear Engineering Air Force Institute of Technology Dec 1976
Thesis: "Thermal Neutron Damage in Bipolar PNP Transistors"
MS Economics South Dakota State University May 1975
Research Paper: "Social Cost of Alcohol-Related Motor Vehicle Accidents in the State of South Dakota in 1973"
BS Physics Brigham Young University May 1971
(Inverse chronological order)
Lecturer – Utah Valley University – Computer Science and Engineering - Since 8/2011
Lecturer – Utah Valley University – Information Systems and Technology - 8/2010-6/2011
Associate Professor – Brigham Young University Hawaii- Comp. Info. Science Dept. –6/2008-8/2010
Chair of our new Information Technology Program, and full time instructor. See course list below.
Assistant Professor – Brigham Young University Hawaii- Computer Science Dept. - 1/2003-6/2008
Courses taught – Computer Programming 1, Computer Organization, Computer Architecture, Robotics, Computer Graphics, Computer Ethics, Introduction to Linux Administration, Hardware Repair and Diagnostics, Computer Networking, Computer Network Operating System
Program Manager – Productivity Analysis (Motorola, International SEMATECH)– 8/2000-12/2002
Managed a team of ten in developing and exploiting an economic model of the semiconductor industry, simulation models of fully automated advanced semiconductor processing facilities, cost models of next generation processes, and managing $2.5M in university research projects, co-sponsored with Semiconductor Research Corporation (SRC).
Project Manager – Manufacturing Planning, Semiconductor300 (Dresden, Germany) –1/98-8/2000
Produced factory designs for cost analyses for 200mm and 300mm factories to show potential productivity gain from 300mm production. Produced simulation models of the SC300 pilot line and litho cluster tools to facilitate planning of equipment purchases, optimizing FOUP conversion scenarios, understanding capacity and cycle time issues, and facilitating equipment purchase decisions. Analyzed material flow in the SC300 pilot line and a comparison of factory layout designs, “Farm and Work Flow.” Published 82 weekly issues of an Expatriate news letter and ten corporate news notes, to help with cultural adjustment issues. First Motorola Expatriate.
Factory Modeling and Simulation Engineer - Senior Staff Member - Motorola - 2/95-1/98
Accomplished and validated factory flow simulations of three Motorola IC factories using AutoSched and ManSim as well as factory cost analysis in support of Motorola's planned VLSI factory using 300mm wafers. Demonstrated a 12% increase in output and reduced cycle time through more natural product flow in existing fab. Accomplished and analyzed layouts for pilot and production factories using AutoCad and CIM Technology’s Factory Flow, AutoCad extensions. Accomplished capacity modeling for both high performance microprocessor and DRAM flows using 300mm tool sets.
Future Factory Design Engineer - Senior Member Technical Staff - SEMATECH - 8/91-2/95
Accomplished analysis for, and co-authored two SEMATECH technical reports identifying the risks and benefits of the transition of VLSI microelectronics production to larger wafer sizes. Accomplished economic analysis for high level microelectronics industry and Equipment supplier committee to develop competitive tool performance requirements. Published the projected competitive benefits of SOI production providing member companies additional infrastructure for a simpler, smaller, faster VLSI technology. Developed computer tools for sensitivity analysis of VLSI factory costs and flow dynamics including yields, utilization, capital costs, batching, cycle time. Managed a contract to quantify the value of Computer Integrated Manufacturing (CIM) systems in the microelectronics industry
Officer, United States Air Force - 6/28/71 to 8/1/91 (final rank Lieutenant Colonel)
Air Force Liaison to SEMATECH, US Microelectronics Manufacturing Consortium (2 years)
Promoted utilization of DOD funded Microelectronics Manufacturing Science and Technology (MMST) by SEMATECH which has become the foundation of the current SEMATECH Computer Integrated Manufacturing efforts saving millions of dollars. MMST demonstrated a three day cycle time for 0.35um double metal level CMOS. Developed, executed, presented and published semiconductor factory modeling software evaluation procedures for member companies. Helped develop the "SEMATECH Future Factory Program Guide that resulted in funding for the SEMATECH Future Factory Program.
Leader, Radiation Effects on VLSI Electronics Group at Defense Nuclear Agency (4 years)
- Managed $12M/year program developing radiation tolerant VLSI electronics.
- Advised DOD on microelectronics development priorities.
- Removed metal contaminants from SIMOX implants through tool retrofit.
Chief, Radiation Effects on VLSI Electronics Section, Weapons Laboratory (3 years)
- Managed eighteen scientists and engineers.
- Developed and characterized radiation tolerant VLSI microelectronics.
Associate Member of Technical Staff, Sandia National Laboratories (2 years)
Center For Radiation Hardened Microelectronics
- Defined VLSI process flows and monitored through process flow.
- Characterized the rapid recovery of MOS devices from pulsed irradiation
Particle Beam Fusion Diagnostics Division
- Characterized negative ion leakage currents in magnetically insulated transmission lines for particle beam fusion applications
Patents and Publications
Patent Disclosures Submitted Eleven
Defensive Publications Made Six
Patents Pending Four
Patents Granted two
- Patent Number 6,420,243 B1 “Method for producing SOI wafers by delamination” July 16, 2002
- Patent Number 6,491,451 “Wafer processing equipment and method for processing wafers” 12/10/02
Publications in Journals and Proceedings
1. Stanley, Fairclough, deBry, Kamali - Sarvestani, “Using A Simple Emulated Computer To Facilitate Understanding In Introductory Computer Programming And Computer Organization / Architecture Classes”, The Journal of Computing Sciences in Colleges, Volume 29, Number 2, Pages 60-66, Dec, 2013.
2. Barlow, Hossley, Stanley, “Use of Interactive Logic Simulation Software to introduce Data Path and Control concepts in Introductory Architecture Courses”, The Journal of Computing Sciences in Colleges, Volume 29, Number 2, Pages 4-16, Dec, 2013.
3. Stanley, Chetty, Styles, Jung, Duarte, Lee, Gunter, Fife, “Teaching Computer Architecture Through Simulation (A Brief Evaluation of CPU Simulators)”, The Journal of Computing Sciences in Colleges, Volume 27, Number 4, Pages 37-44, April, 2012.
4. Stanley, Calvo, “Rhythm Learning with Electronic Simulation,” SIGITE’09, October 22–24, 2009, Fairfax, Virginia, USA
5. Stanley, Colton, “Six Years of Sustainable IT Service Learning,” SIGITE’09, October 22–24, 2009, Fairfax, Virginia, USA
- Stanley, Kim, Chan, Zheng, Fife, "Experiences in Teaching Computer Architecture," Journal of Computing Sciences in Colleges Volume 24, Issue 4, Pages 46-52, April, 2009
- Stanley, Wong, Prigmore, Benson, Fishler, Fife, and Colton , (2007 June) “From Archi Torture to Architecture: Undergraduate Students Design and Implement Computers using the Multimedia Logic Emulator”. Computer Science Education, Vol. 17, Num. 2, June 2007, p. 141-152, ISSN Print 0899-3408 ISSN Online 1744-5175. Special Issue on teaching hardware-software fundamentals.
- Stanley, Xuan, Fife, Colton (Jan 2007) “Simple Eight Bit, Emulated Computers for Illustrating Computer Architecture Concepts and Providing a Starting Point for Student Designs,” Ninth Australasian Computing Education Conference (ACE2007), Vol. 66, p.141-146,http://crpit.com/Vol66.html
- Stanley, Prigmore, Mikolyski, Embrey, Fife, (2007 June) “Pedagogic Value in Understanding Computer Architecture of Implementing the Marie Computer from Null and Lobur in the Logic Emulation Software, Multimedia Logic”, Proceedings of the Workshop on Computer Architecture Education, 34th International Symposium on Computer Architecture, p 66-71. http://www4.ncsu.edu/~efg/wcae2007.html
10. Stanley, Wong (2005 June) "An emulated computer with assembler for teaching undergraduate computer architecture," Proceedings of the Workshop on Computer Architecture Education, 2005
11. Fife, Stanley, Segal, Kumar, (2005) "A Comparison of Robots Used in a Senior Level Robotics Course and Senior Projects," 9th Annual Global Chinese Conference on Computers in Education, 2005
12. Stanley, (2004) “Bringing bit, bytes, devices and computers to life with designs in multimedia logic”, Proceedings of the 5th Conference on Information Technology Education, p. 267-267
13. Stanley, Markle, Van Eck, Cusson, Purdy, Stanley, (2003) “Cost and revenue impact of advanced process control (APC) with an emphasis on run-to-run control (R2R)," Proc. SPIE Vol. 5044, p. 130-138,
14. Stanley, Campbell, Rust, Cheatham, Maia, Wright, Harris, Norman, Rohrer, Harris, Lebaron, Johnson, Kirby, Carson (2001) “Linking an AutoSched AP Process Model with an AutoModTransport Model Using MCM in a 300mm Fab”, Proceedings of the Brooks Automation Symposium, Salt Lake City
15. Schulz, Stanley, Renelt, Sturm, Schwertschlager, (2000) “Simulation Based Decision Support for Future 300mm Automated Material Handling”, Proceedings of the 32nd Winter Simulation Conference, p. 1518-1522.
16. Stanley, Schulz (2000) “Two Methodologies For Quickly Sizing Factories With Discrete Event Simulation, And Observations of Resonance and Chaos in Semiconductor Manufacturing”, Proceedings of the International Conference on Modeling and Analysis of Semiconductor Manufacturing (MASM)
17. Stanley, Schulz (2000) “An Example The Tactical Application of Simulation – Support of FOUP Conversion in a 300mm Pilot Line,” Proceedings of the International Conference on Modeling and Analysis of Semiconductor Manufacturing (MASM), May 10, 2000.
18. “Integrated Metrology, The Next Logical Step for Advanced Wafer Processing”, ISSM ’99, Nov 13, 1999
19. “Litho Cluster With Integrated Metrology – The Next Step Toward Continuous Flow Manufacturing”, SPIE Microelectronic Manufacturing, September 23, 1999
20. "Thermal Preprocessing to Shorten Flows, Simplify Lithography, and Radically Reduce Processing Cycle Time," IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part C: Manufacturing, Page 85, Vol 19, Num 2, April 1996.
21. "Batchless Factory Concept For Very Short Cycle Time Semiconductor Manufacturing," 17th IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings, IEEE Cat. # 95CH35864, October 2-4, 1995.
22. El-Kareh, Chen, Stanley, (1995) "Silicon On Insulator - An Emerging High Leverage Technology," IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part A, Vol 18, #1, March 1995.
23. "SOI For Mainstream VLSI - Another Look at the Economic Incentive," Invited Paper, Proceedings of the 6th International Symposium on Silicon-On-Insulator Technology and Devices, ECS Volume 94-11, May 1994
24. "Materials Requirements for Future Semiconductor Technology," Invited Paper, Co-authors - PK Vasudev & Tom Seidel, Semiconductor Silicon/1994, ECS Volume 94-10, May 1994
25. "Revenue Sensitivity to Yield and Starting Wafer Cost in SOI SRAM Production," Proceedings of the Second International Symposium on Semiconductor Wafer Bonding, November 1993
26. "Cost Analysis for a Multiple Product / Multiple Process Factory: Application of SEMATECH's Future Factory Design Methodology," Proceedings of the 4th Annual Advanced Semiconductor Manufacturing Conference and Workshop, October 19-20, 1993
27. Stanley, (1993) "Revenue Sensitivity To Yield And Starting Wafer Cost In SOI SRAM Production," ECS Extended Abstracts, Vol 93-1, May 16-21, 1993
28. Stanley (1992) "Revenue Potential From SOI Production," Proceedings of the 1992 IEEE International SOI Conference, ISBN: 0-7803-7439-8
29. "The State-of-the-Art in Silicon On Insulator Technologies," IEEE Transactions on Nuclear Science, Vol NS-35, No. 6, December 1988
30. "The Implications of Operational Bias on Survivability in Long-Term Low-Dose Environments," Government Microcircuit Applications Conference - Digest of Papers, Volume XI, November 1985
31. Stanley et all, (1985) "The Effect of Operating Frequency in the Radiation Induced Build-Up of Trapped Holes and Interface States in MOS Devices," IEEE Transactions on Nuclear Science, Vol NS-32, No. 6, December 1985
32. Stanley (1985) "Transient Annealing in MOS Devices," Proceedings of the first Hardened Electronics And Radiation Technology (HEART) Conference, Government Classified
33. "Rapid Anneal of Pulsed Radiation Damage in MOSFETs," Government Microcircuit Applications Conference (GOMAC), 1982 Digest of Papers – Government classified
34. Stinnet, Stanley, (1982) "Negative Ion Formation In Magnetically-Insulated Transmission Lines," Journal of Applied Physics, May 1982
35. Stanley, Stinnet (1982) "Measurement of Magnetically-Insulated Line Voltage Using A Thomson Parabola Charged Particle Analyzer," NBS Special Publication 628, Measurement of Electrical Quantities in Pulse Power Systems, June 1982
36. Stanley, Vail (1997) "Thermal Neutron Damage in Bipolar PNP Transistors," IEEE Transactions on Nuclear Science, Vol NS-24, No. 6
37. SEMATECH Technical Reports
38. “300 mm Factory Simulation Modeling Results Summary (First Half of 2002)”, Sept 23, 2002, TTID 02094306AENG
39. “Cost and Revenue Impact of Advanced Process Control (APC)”, June 26, 2002, ID 18984
40. “Comparative Analysis of 300 mm Automated Material Handling Systems (AMHS)”, February 26, 2002, TTID: 02024249AENG
41. “Simulation Models of Advance Automated Material Handling Systems” November 1, 2001, TTID: 17514TD
42. “Automated Material Handling (AMH) Benefit Quantification Report”, June 27, 2001, TTID: 01064128AENG
43. "SEMATECH Large Wafer Perspective," September 30, 1994, TR 94062414A
44. "Large Wafer Study Committee Final Report," October 21, 1993, SEMATECH Confidential
45. "Benchmarking Semiconductor Wafer Fabrication Modeling Tools," July 28, 1992, TR 92051145A, SEMATECH Confidential
Government Technical Reports
46. "The Effect Of Operating Frequency In The Radiation Induced Build-Up Of Trapped Holes And Interface States In MOS Devices," AFWL TR 86-12
47. "PONY EXPRESS Analytical Results," AFTAC-TR-80-4, 6 February 1980. Government Classified
48. "Debris Sampling," AFTAC-TR-77-6, 20 December 1977, Government Classified
49. "Thermal Neutron Damage in Bipolar PNP Transistors," AFWL-TR-77-168, December 1977.
Thesis and Dissertations
50. "The Effect Of Operating Frequency In The Radiation Induced Build-Up Of Trapped Holes And Interface States In MOS Devices," Doctoral Dissertation, University of New Mexico, July 1985
51. "Thermal Neutron Damage in Bipolar PNP Transistors," Thesis, Air Force Institute of Technology, December 1976.
52. Thesis (SDSU), "Social Cost of Alcohol-Related Motor Vehicle Accidents in the State of South Dakota in 1973," April 1975.
Other Technical Publications
53. “AutoSimulations Accelerated Processing (ASAP): A Benchmark Against Tyecin Systems ManSim,” Enterprise Modeling News, Published Quarterly by Motorola Manufacturing Systems, Vol. 7 Num. 1., Winter 1996.
54. “Investigating the Relationship of Cycle Time with Factory Loading and Tool Availability: An Application of ASAP,” Enterprise Modeling News, Published Quarterly by Motorola Manufacturing Systems, Vol. 7 Num. 1., Winter 1996.
55. "Estimating Revenue Potential From SOI Production," Semiconductor International, March 1993
56. "DIY: Build a MIDI Interface for the Sound Blaster Card," Electronic Musician Magazine, November 1991
57. "Recent Advances in Silicon-on-Insulator Technologies," Solid State Technology, November 1990 (Guest Editorial) (Republished in Japanese Edition in January 1991.)
58. "A Super Intelligent, But Inexpensive, Peripheral For Heath Computers," REMark - Official Magazine For Users of Heath/Zenith computer equipment, July 1985
Oral Technical Presentations at Conferences
1. “Using A Simple Emulated Computer To Facilitate Understanding In Introductory Computer Programming And Computer Organization / Architecture Classes”, 22nd Rocky Mountain CCSC, Rapid City, South Dakota, Oct11-12, 2013.
2. “Use of Interactive Logic Simulation Software to introduce Data Path and Control concepts in Introductory Architecture Courses”, 22nd Rocky Mountain CCSC, Rapid City, South Dakota, Oct11-12, 2013.
3. “Teaching Computer Architecture Through Simulation (A Brief Evaluation of CPU Simulators)”, 223nd Southwestern CCSC, Canyon, Texas, April 20-21, 2012
4. “Rhythm Learning with Electronic Simulation,” SIGITE’09, October 22–24, 2009, Fairfax, Virginia, USA
5. “Six Years of Sustainable IT Service Learning,” SIGITE’09, October 22–24, 2009, Fairfax, Virginia, USA
6. “Simple Eight Bit, Emulated Computers for Illustrating Computer Architecture Concepts and Providing a Starting Point for Student Designs,” Ninth Australasian Computing Education Conference (ACE2007)
7. “Pedagogic Value in Understanding Computer Architecture of Implementing the Marie Computer from Null and Lobur in the Logic Emulation Software, Multimedia Logic”, Proceedings of the 2007 Workshop on Computer Architecture Education
8. “Linking an AutoSched AP Process Model with an AutoModTransport Model Using MCM in a 300mm
Fab”, Proceedings of the Brooks Automation Symposium 2001, Salt Lake City, June 2001
9. “A Measuring and Modeling Point of View, Equipment and Non-Equipment Productivity Improvement”, Industry Strategy Symposium, Pebble Beach, CA,Jan 2002
10. “Simulation Based Decision Support for Future 300mm Automated Material Handling”, Proceedings of the Winter Simulation Conference, Orlando, Dec 2000
11. "Batchless Factory Concept For Very Short Cycle Time Semiconductor Manufacturing," International Electronic Manufacturing Technology Conference, Austin, TX, Oct. 4, 95
12. "Silicon-On-Insulator - An Emerging High-Leverage Technology," 44th Electronic Components & Technology Conference, Washington, DC, May 1994 (Selected Outstanding Paper of session)
13. "SOI For Mainstream VLSI - Another Look at the Economic Incentive," Invited Paper, 6th International Symposium on Silicon-On-Insulator Technology and Devices, San Francisco, CA, May 1994
14. "Revenue Sensitivity To Yield And Starting Wafer Cost In SOI SRAM Production," ECS Conference, Honolulu, Hawaii, May 17-18, 1993
15. "Revenue Potential From SOI Production," 1992 IEEE International SOI Conference, Ponte Vedra Beach, FL, October 8, 1992
16. "The State-of-the-Art in Silicon On Insulator Technologies," IEEE Conference on Nuclear And Space Radiation Effects, Portland, Oregon, July 1988
17. "A Simple Model For Time And Bias Dependent, Radiation Induced, Interface State Build-Up And Hole Detrapping", IEEE Conference on Nuclear And Space Radiation Effects, Providence, Rhode Island, July 1986
18. "Interfacing Heath and Atari Computers," National Conference of the Capital Heath Users' Group (CHUG), Crystal City, Virginia, Nov. 1985
19. "Insights From Alternating Bias Experiments on the Radiation Caused Build-Up of Interface States in MOS Devices," IEEE Semiconductor Interface Specialists Conference, Ft. Lauderdale, Florida, Dec. 3, 1985
20. "The Implications of Operational Bias on Survivability in Long-Term Low-Dose Environments," Government Microcircuit Applications Conference, Orlando, Florida, November 1985
21. "Effects of Operating Frequency on Total Dose Response," NASA/SD Space Parts Working Group - Hardness Assurance Committee Meeting, New Orleans, Louisiana, Oct. 10, 1985 (Invited Presentation)
22. "The Effect of Operating Frequency in the Radiation Induced Build-Up of Trapped Holes and Interface States in MOS Devices," IEEE Conference on Nuclear And Space Radiation Effects, Monterey, California, July 1985
23. "Rapid Anneal of Pulsed Radiation Damage in MOSFETs," Government Microcircuit Applications Conference (GOMAC), Orlando, Florida, Nov. 1982
24. "Transient Annealing in MOS Devices," Hardened Electronics And Radiation Technology (HEART) Conference, Las Vegas, Nevada, July 1982
25. "Measurement of Magnetically-Insulated Line Voltage Using A Thomson Parabola Charged Particle Analyzer," Workshop On Measurement Of Electrical Quantities In Pulse Power Systems, National Bureau of Standards, Boulder Colorado, March 2, 1981
Professional Society Service
ACM/SIGCSE Symposium - Session Chair March 2012
ACM/SIGCSE Symposium - Session Chair Feb 2005
AEC/APC Symposium XIV - Session Co-chair Sept 2002
Electrochemical Society Meeting – Co-chairman May 1994
Institute of Electrical and Electronic Engineers (IEEE)
Co-chairman Session of IEEE SOI/SOS Workshop October 1994
Co-chairman International Electron Device Meeting December 1989
Subcommittee International Electron Device Meeting December 1989
Session Chair Nuclear & Space Rad Effects Conf. July 1987
Session Chair Hard Elec. & Radiation Tech. Conf. July 1986
Government Microcircuit Applications Conference
Steering Committee 1986 to 1989
Session Chairman November 1987
Electronic Industries Association, Space Electronics Conference
Steering Committee November 1986
American Nuclear Society - Chapter Secretary Jun 1975 - Jun 1977
Awards and other recognition
Senior Member of IEEE June 2013
Promoted to Associate Professor March 2008
Motorola Manufacturing Technology Award (1st 300mm Manufacturing) July 2000
Silver Quill Award, Motorola May 1996
Promoted to "Senior Member of Technical Staff," SEMATECH May 1994
Defense Meritorious Service Medal, United States of America 1985-1989
Meritorious Service Medal, United States of America 1980-1985, 1989-1991
Outstanding Technical Manager, Air Force Weapons Laboratory 1984
Laboratory Associate, Sandia National Laboratories 1980-1982
Air Force Commendation Medal, U S Air Force 1977-1980
Distinguished Graduate, Missile Combat Crew Training July 1971
Eagle Scout, Boy Scouts Of America
Part-Time College-level Teaching Experience
Instructor University Of Virginia Electrical Engineering Review
A nine-hour review of electronics for electrical engineers preparing to take
the professional engineering exam (taught four semesters).
Instructor George Mason University Digital Circuit Analysis ECE431
A three credit hour class on design and analysis of digital logic circuits.
Short Courses & other technical training
Consumer Electronics Bell & Howell Schools
Computer Technology National Technical Schools
VLSI Design Tools and Technology Sandia National Labs
Microprocessor Technology Sandia National Labs
VLSI Technology McGraw Hill
VLSI Technology University of Texas
Flip Chip Technical Seminar 44th Electronic Components & Technology Conference
Radiation Effects in VLSI Circuits 6 IEEE NSREC Short Courses
VLSI Reliability Issues IEEE IEDM Short Course
AutoSched 1 & 2 & AutoMod AutoSimulation Inc.
AutoCad Vision Graphics
CompTIA A+ and Nework + Certified 2004
Power User of PCs, Macintoshs, and Unix workstations
Developed software applications in Compiled BASIC, Visual BASIC, FORTRAN, C, UNIX, AWK, Pearl
Daily User of MS EXCEL, Power Point, Word, Access and Word Perfect
Trained in WorkStream CIM System
Power User of SEMATECH's Cost Resource Model, ManSim, AutoSched, ASAP, SAS, Flexsim Fabmodeler
Electronics Hobby - Assembled 25” Heathkit Color TV, Heathkit H89 computer, Heathkit Thomas Organ, Oscilloscope, Multimeters, Video Game Machine, Hero Robot, Digital Clock, Stereo Receiver/Amplifier, LCD Display Watch, Calculator, digital design console. Designed and built: Switch to parallel port interface, Midi Interface, Wireless remote control for robot.